1. Course Details

  • Level: Seniors and Graduates
  • Prerequisites: Computer Organization and Logic Design or instructor’s approval
  • Lecture Times:  TBA
  • Student Study Hours Per Week: 9
  • Contact Hours Per Week: 3
  • Private Study Hours Per Week: 6
  • AY / Semester:  2004– 2005/ Spring
  • Professor:  Dr. I. Damaj
  • Contact Details: TBA
  • Professor's Website: http://www.idamaj.net
  • Summary of Assessment Method:  Project, 1 Quiz, 2 Assignments (Short Research Papers Review), and a Final
  • Hardware Devices: TBA
  • Software Packages: MorphoSys reconfigurable computer emulator, VHDL, Handel-C high-level HDL compiler (DK design suite), Xilinx ISE. Haskell
  • Textbook:NA – Mainly From Research Material, References, and Technology Handbooks
  • References: D. Gajski, “High-Level Sythesis, Introduction to Chip and System Design” Kluwer, 1992. R. Seals, “Programmable Logic: PLDs and FPGAs,” Macmillan, 1997. Logic and Computer Design Fundamentals, 2nd edition updated, M. Morris Mano and Charles R. Kime, Prentice Hall, 2001..

2. Aims of the Course:

This course presents the foundations of hardware/software co-design stressing the role of a computer scientist in modeling, formalizing and implementing various hardware architectures. This course also presents reconfigurable computers as a soft-hardware that can be reprogrammed and synthesized through high-level tools. Also, it shows how to apply such programmable architectures to solving computationally-intensive problems (mainly cryptography). This includes hardware platforms and software support systems for reconfigurable computing using field programmable gate arrays. This course will examine state-of-the-art systems that dynamically change their configuration with changing data sets and algorithm needs. Topics covered in the course include the basic concept of hardware design, reconfigurable computing and its modes of operation (static vs. dynamic reconfiguration), examples of successful RC applications, existing design methodologies and formalisms, existing architectures, hardware/software co-design tools, and future trends. The course will lay a foundation for students who are interested in further studies in hardware/software codesign and reconfigurable computing – hardware synthesis and chip design are active areas of research!

3. Short Description:

This course is of 5 chapters divided into 15 weeks. The student should be aware of the importance of revising the material on first come first serve basis. Prerequisites of this course include Computer Organization, Logic Design and C programming language. The assessment is done by reviewing 2 short research papers (Ws 4 and 10), 1 design project (proposal due by W8, presentations in Ws 14 and 15), a quiz (W9), and a final exam.

Details Topic Chapter No. Assessment
Week 1 Introduction and Motivation 1
Week 2 - 8 Hardware/Software Co-design, and Reconfigurable Computing Architectures
2.1 Hardware Design and Programmable Logic
2.2 Programmable Logic Devices, General Architectures, SPLDs and CPLDs
2.3 Programmable Logic Devices, FPGAs
2 Research Assignment I (W4)
Useful Links:
1. The Task of the Referee
2. Writing Technical Articles
3. Research Award Judging Criteria
Quiz (W6) View Grades
Weeks 9 - 10 High-Level Hardware Synthesis 3 Project Proposal (W9)
Week 11 - 13 Case Study I: Handel-C High-Level HDL 4
Week 14 - 15 Case Study II: Synthesis of Cryptographic Algorithms for FPGAs 5 Projects Presentations (W14 and W15)

5. Assessment of the Course

Assignments and Quizes 30%
Project 60%
Final 10%

[May 25, 2005] The Final exam includes chapters 2, 3, and 4. The date of the exam is to be announce by the department office.

[April 20, 2005] The projects' proposals are due on Sunday, 30 April 2005. Early e-mail submissions of proposals are strongly recommended. You will receive a direct reply (acceptance/rejection).

[April 19, 2005] The grades for the quiz are out.

© 2015 - Dr. Issam W. Damaj