Logic Design

Hariri Canadian University

School of Engineering

Electrical and Computer Engineering Department

Logic Design – Course Guide

CCEE 110

1. Course Details:

Course Title:	Logic Design
Level	I
Course Reference	CCEE 110
Lectures	MTWTH 3:00 p.m. - 4:50 p.m.
Room	H205
Laboratory	TBA
Office Hours	TBA
Student Study Hours Per Week	24
Contact Hours Per Week	8
Private Study Hours Per Week	16
Year and Semester	2006 Summer A
Lecturer	Dr. I. Damaj
Contact Details	damajiw[@]hariricanadian.edu.lb - Remove the brackets [ ]
Summary of Assessment Method	Midterm, Project, Laboratory Assignments, and a Final
Textbook	Logic and Computer Design Fundamentals, 3^rd edition updated, M. Morris Mano and Charles R. Kime, Prentice Hall, 2004.

2. Aims of the Course:

This course covers the following topics: logic gates, binary number systems, conversion between number systems, Boolean algebra, Karnaugh maps, combinational logic, digital logic design, flip-flops, programmable logic devices (PLDs), counters, registers, memories, and state machines.

3. Short Description:

This course is of 8 chapters divided into 6 weeks. The student should be aware of the importance of revising the material synchronously with the lectures. The assessment is done by 1 Midterm (week4), lab assignments, and a final exam. Lab emphasizes the use of a schematic entry, the use of a logic simulation design tools, and hardware description languages (mainly VHDL). Lab assignments are design-oriented.

4. Schedule:

Details:	Topic	Chapter No.	Assessment
Week 1	Digital Computers & Information	1
Weeks 1 – 2	Combinational Logic Circuits	2
Weeks 2 – 3	Combinational Logic Design	3
Weeks 3 – 4	Combinational Functions and Circuits	4	Midterm (Week 4)
Week 5	Arithmetic Functions and Circuits	5
Weeks 5 – 6	Sequential Circuits	6
Week 6	Registers and Counters	7
Week 6	Memory Basics	8

5. Assessment of the Course:

Midterm	35%
Project	10%
Lab Assignments	20%
Final	35%

Laboratory

1. Lab. Details:

Course Title:	Laboratory for the course: Logic Design
Student Study Hours Per Week	5 ½
Contact Hours Per Week	2 ½
Private Study Hours Per Week	3
Summary of Assessment Method	6 Assignments
Software Package	EWB, VHDLSimili, Quartis II from Altera, Xilinx ISE Student Version
Operating System	Windows

2. Aims of the Lab:

This lab aims to provide the student with an introductory understanding of practical Logic Design issues. The general concepts to be introduced in this lab will increase the students’ awareness of the available digital hardware design packages

3. Short Description:

This lab introduces EWB (Electronics Work Bench) and VHDL. This includes describing combinational circuits, sequential circuits, registers and counters in structural and behavioral settings. The assessment is done by 4 assignments due in Weeks 3, 4, 5, 6 and a project.

4. Schedule:

Details:	Topic	Assignment due in
Week 1	Software Setup	-
Week 2	Binary Numbers and Basic Logic Operations
Week 2	Combinational Logic Circuits
Week 3	Introduction to VHDL	Assignment I (Week 3)
Week 3	VHDL – Structural and Behavioral Descriptions
Week 4	Arithmetic Functions and Circuits	Assignment II (Week 4)
Week 5	Sequential Logic Circuits	Assignment III (Week 5)
Week 6	Applications	Assignment IV (Week 6)
Week 6	Project	Project (Week 15)

5. Assessment of the Lab:

The lab weighs 30% of the total course grade (4 assignments, a project, and a lab final exam).

Announcements

[June 18, 2006] Chapters 7 and 8, and assignment 4 are posted.

[June 12, 2006] The project details are now available.

[June 12, 2006] Midterm Grades are posted.

[June 9, 2006] Chapters 5 and 6 are posted.

[June 5, 2006] Chapter 4 is posted.

[June 5, 2006] Assignment 3 is posted.

[May 29, 2006] Assignment 2 is posted.

[May 29, 2006] Chapter 3 is posted.

[May 23, 2006] Assignment 1 is posted.

[May 23, 2006] Chapter 2 is posted.

[May 23, 2006] Tuesday's class will be reserved for groups setup. Classes to resume normally on Wednesday.

[May 15, 2006] Chapter 1 is posted.

[May 15, 2006] To use VHDL Simili from Symphony EDA, from the Symphony EDA Licensing Wizard (Start -> All Programs -> Symphony EDA -> VHDL Simili 2.3 -> License Management) you should activate your free license online. Please note that after installing the package, you must replace the file: symphony.lic, in the directory: C:\Program Files\Symphony EDA\VHDL Simili 2.3\Bin with the file: freelic.txt. In other words, delete the existing symphony.lic, and rename freelic.txt to symphony.lic; make sure the new file is not called symphony.lic.txt!

[May 15, 2006] Peter J. Ashenden, VHDL Tutorial, Elsevier Science, 2004.

[May 15, 2006] Every student should install EWB (Multisim is already installed in the lab), Quartes II (You might need to have your hard disk volume number ready for the free license - click to see how to get it), VHDLSimili (From Symphony EDA), and Xilinx ISE 4.2i (Available with the textbook).

[May 15, 2006] Welcome to the course website...