Hariri Canadian University
School of Engineering
Electrical and Computer Engineering Department
Hardware/Software Co-design – Course Guide
CCEE 500
1. Course Details:
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Course Title: |
Hardware/Software Co-design |
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Level |
Graduates |
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Course Reference |
CCEE 500 |
| Prerequisite | CCEE 314 - Embedded System Design |
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Lectures |
MTWTH 12:30 p.m. – 2:20 p.m. |
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Student Study Hours Per Week |
24 |
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Contact Hours Per Week |
8 |
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Private Study Hours Per Week |
16 |
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Year and Semester |
2005 - 2006 Summer A |
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Lecturer |
Dr. I. Damaj |
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Contact Details |
damajiw[@]hariricanadian.edu.lb - Remove the brackets [ ] |
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Summary of Assessment Method |
1 Midterm, Term project, Assignments, and a Final |
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Textbook |
Embedded System Design: A Unified Hardware/Software Introduction, Frank Vahid and Tony Givargis John Wiley & Sons; ISBN: 0471386782. Copyright (c) 2002. |
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References |
C. A. R. Hoare, Communicating Sequential Processes. (Prentice-Hall, 2004).
Introduction to Parallel Processing: Algorithms and Architectures. Behrooz Parhami, Plenum 1999.
S. Thompson Haskell the Craft of Functional Programming, (Prentice-Hall, 1998)
D. Gajski, “High-Level Sythesis, Introduction to Chip and System Design” Kluwer, 1992.
Hachtel, Somenzi, "Logic Synthesis and Verification Algorithms" Kluwer, 1996.
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| Hardware Packages | CoolRunner CPLDs |
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Software Packages |
C++/Visual C++, VHDL, Verilog, Haskell, FDR CSP Tool. |
2. Aims of the Course:
This course goes into the details of modern hardware/software co-design process. We build on the knowledge in system design that a student has acquired during the embedded system design, computer organization and architecture, and logic design courses. The material of this course presents advanced modeling techniques, modern rapid prototyping methodologies, and role of engineering formal methods in designing hardware. The practical aspects of this course include gaining experience in modeling software packages and checkers, various hardware description language (VHDL, Handel-C, LAVA, SystemC, etc.) and hardware design tools, and running designs on the available CoolRunner CPLDs.
3. Short Description:
This course is of 6 chapters divided into 6 weeks. The student should be aware of the importance of revising the material synchronously with the lectures. Students should be also aware of the new style of study required in a graduate school. Topics addressed in this course include, but not limited to, introduction to system design, state machine and concurrent process models, logic synthesis, high-level synthesis, and IC technology. The assessment is done by 1 midterm (Week 4), assignments, a term research project, and a final exam.
4. Schedule:
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Details: |
Topic |
Chapter No. |
Assessment |
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Weeks 1 - 2 |
1 |
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Weeks 2 - 4 |
2 |
Assignment |
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Week 5 |
High-level Synthesis | 3 | |
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Week 6 |
Logic Synthesis |
4 |
Midterm |
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Week 6 |
IC Technology |
5 |
Project |
5. Assessment of the Course:
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Midterm |
20% |
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Term Project |
30% |
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Assignments |
20% |
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Final |
30% |
Announcements
[June 18, 2005] Chapter 5 is posted.
[June 15, 2005] Chapter 3 is posted.
[May 28, 2005] Chapter 2 is posted.
[May 25, 2005] There will be no extra session this Friday at 8:00 a.m. classes will resume normally from Monday.
[May 23, 2005] Functional programming and CSP notation presentations are to start directly after chapter 2 material.
[May 23, 2005] Chapter 1 is posted.
[May 23, 2005] Welcome to the course website...