1. Course Details

  • Level: Seniors
  • Prerequisites: CPEG 340 Embedded System Design
  • Lecture Times:  MW 11:00 a.m. – 12:15 a.m. (Section 1)
  • Classroom: A 208
  • AY / Semester:  2010 – 2011 / Spring
  • Professor:  Dr. I. Damaj
  • Contact Details: idamaj@auk.edu.kw
  • Course Detailed Site:  http://lms.auk.edu.kw
  • Professor's Website: http://www.idamaj.net
  • Summary of Assessment Method:  A Midterm, pop quizzes, assignments, project, and a final exam
  • Textbook: Embedded System Design: A Unified Hardware/Software Introduction, Frank Vahid andTony Givargis John Wiley & Sons; 2002.
  • Software Tools: Quartus, Hugs98, FDR, LabVIEW
  • Hardware Devices: FPGA Systems DE2-70, DE4-230, RC-10, and RC-2000
  • References: Digital Fundamentals, Thomas Floyd, 10th edition, 2010 A Practical Introduction to Hardware/Software Codesign, Schaumont, Patrick R. 1st Edition, 2010 Haskell: The Craft of Functional Programming, Simon Thompson, 3rd Edition, 2012 Concurrent and Real-time Systems: the CSP Approach, Steve Schneider, 1999 Communicating Sequential Processes, C. A. R. Hoare, Prentice-Hall, 2004 Logic Synthesis and Verification Algorithms, Hachtel, Somenzi, Kluwer, 1996

2. Catalog Description

Design models: state machines, concurrent process models, dataflow, communicating sequential processes (CSP), etc. Design partitioning, co-synthesis, co-simulation, co-design. Transformational co-design, formal models, correctness. Functional programming in HW design, concurrency, synthesis of parallel algorithms. HW Compilers. Prerequisite: CPEG 340 Embedded System Design.

3. Student Learning Outcomes

At the end of this course the students will be able to:

  • Design using different design models; FSMs, HCFSMs, PSMs, etc.
  • Design using concurrent process models and CSP descriptions
  • Implement hardware designs using high-level tools
  • Use FPGA-based reconfigurable systems; CompactRIO, DE2-70, DE4-230, RC-10, and/or RC-2000
  • Implement functional specifications under Haskell
  • Understand basic transformational co-design procedure to map functional programs onto FPGAs
  • Understand the organization and architecture of reconfigurable computing systems; coarse-grained systems such as the MorphoSys, CPLDs, FPGAs, etc.
  • Understand high-level synthesis, design partitioning, co-synthesis, verification and co-simulation techniques, and the reuse of IP-cores
Details Topic Chapter No. Assessment
Week 1 Introduction to Hardware/Software Co-design 1
Weeks 2 – 6 Computation Models 2 Assignment
Weeks 7 – 10 Communicating Sequential Processes 3 Midterm
Weeks 10 – 11 Functional Programming in Hardware Design 4
Week 12 Presentations - Term Paper
Week 13 Reconfigurable Computing Systems 5
Week 14 Co-design Technology 6
Week 15 Presentations - Project

5. Assessment of the Course

Attendance and Pop quizzes 5%
Midterm 25%
Assignment and Term Paper 25%
Project 20%
Final 25%