Department of Electrical and Computer Engineering
CPEG 210: Digital Logic Design
Course Guide
1. Course Details
- Level: Juniors
- Prerequisites: CSIS 120 Computer Programming I
- Lecture Times: UTR 09:00 a.m. – 09:50 a.m. (Section 1), UTR 10:00 a.m. – 10:50 a.m. (Section 2)
- Classroom: A 208
- Lab Times: U 03:30 p.m. – 06:30 p.m. (Section 1), U 12:00 p.m. – 03:00 p.m. (Section 2)
- Lab: Digital Systems Laboratory (B 108)
- AY / Semester: 2010 – 2011 / Fall
- Professor: Dr. I. Damaj
- Contact Details: idamaj@auk.edu.kw
- Course Detailed Site: http://lms.auk.edu.kw
- Professor's Website: http://www.idamaj.net
- Summary of Assessment Method: 2 quizzes, pop quizzes, assignments, lab experiments, project and presentation, and a final exam
- Textbook: Digital Design, 4th edition, M. Mano and M. Ciletti, Pearson International Edition, 2007.
- Software Tools: MultiSim, Quartus II, and Debug Assembler
- References: Digital Fundamentals with PLD Programming: 1/e 2006, Prentice Hall, Thomas Floyd.
2. Catalog Description
Number systems and codes, Boolean algebra, minimization methods, combinational circuit design and analysis, arithmetic blocks, programmable logic, latches and flip-flops, sequential logic design, state machines, registers, counters, memory elements, logic synthesis, high-level synthesis, an introduction to VHDL. A lab component is included in this course. Prerequisite: CSIS 120 Computer Programming I; 4 Credit hours.
3. Student Learning Outcomes
At the end of this course the students will be able to:
- Apply number system conversions, typically related to binary system
- Simplify Boolean expressions using basic theorems and properties of Boolean Algebra
- Apply gate-level minimization techniques
- Design combinational arithmetic and logic circuits
- Design synchronous sequential logic circuits
- Use Registers and Counters
- Implement Logic Circuits using Programmable Logic Devices
- Understand basic memory organization
4. Schedule
| Details | Topic | Chapter No. | Assessment |
|---|---|---|---|
| Week 1 - 3 | Digital Systems and Binary Numbers | 1 | |
| Weeks 3 – 4 | Boolean Algebra and Logic Gates | 2 | |
| Weeks 4 – 5 | Gate-level Minimization | 3 | Quiz I (Week 6) |
| Weeks 6 – 7 | Combinational Logic | 4 | |
| Week 8 - 11 | Synchronous Sequential Logic | 5 | Quiz II (Week 11) |
| Week 12 - 13 | Registers and Counters | 6 | |
| Week 14 - 15 | Memory and Programmable Logic | 7 | Project Due |
5. Laboratory Experiment Topics
- Basic Logic Gates, Sum of Products, and Product of Sums
- Technology Mapping to NAND Gates
- Combinational Circuits (Adders, Comparators, etc.)
- Latches and Flip-Flops
- Registers and Counters
- Timing Circuits
Mini Project: Applications using 7-Segment Displays
Experiment Pattern: Software Simulation (HDL and/or Schematic) and Hardware Implementation
6. Assessment of the Course
| Attendance | 5% |
| Pop quizzes and assignments | 5% |
| Quiz I | 15% |
| Quiz II | 20% |
| Laboratory | 25% |
| Final | 35% |
7. Announcements
[Jan 16, 2011] Topic 7 material is now complete on Moodle and appears as follows:
R9: Reference Chapter - Get your copy of the chapters available on the S: drive under CPEG 210.
Homework Set 7: The numbers you are responsible for in the textbook are: 7.17, 7.18, 7.19, 7.20, 7.21, 7.22, 7.23, 7.24, 7.25, and 7.28
[Jan 10, 2011] Topic 6 material is now complete on Moodle and appears as follows:
R8: Reference Chapter - Get your copy of the chapters available on the S: drive under CPEG 210.
Homework Set 6: The numbers you are responsible for in the textbook are: 6.1, 6.2, 6.3, 6.4, 6.5, and 6.21
[Jan 5, 2011] Topic 5 material is now complete on Moodle and appears as follows:
Homework Set 5: The numbers you are responsible for in the textbook are: 5.2, 5.4, 5.5, 5.6, 5.12, and 5.15.a
R7: Reference Chapter - Get your copy of the chapters available on the S: drive under CPEG 210.
Quiz II is on Sunday, 9th of January at 2:00 p.m. in the DSL Lab. Material includes Chapters 4 and 5 (Wherever we reach).
Quiz II make-up is on Sunday, 16th of January at 2:00 p.m. in the DSL Lab. Material includes Chapters 4 and 5. The exam is open book.
[Dec 15, 2010] Topic 4 material is now complete on Moodle and appears as follows:
Homework Set 4: The numbers you are responsible for in the textbook are: 4.1, 4.2, 4.3, 4.4, 4.6, 4.17, 4.18, 4.21, 4.23.a, 4.24, and 4.25
R5 and R6: Reference Chapters - Get your copy of the chapters available on the S: drive under CPEG 210.
[Nov 23, 2010] Topic 3 material is now complete on Moodle and appears as follows:
Homework Set 3 The numbers you are responsible for in the textbook are: 3.1, 3.2, 3.3, 3.4, 3.5, 3.6, 3.7, 3.8, 3.15, 3.17, and 3.21
R4: Reference Chapter Get your copy of the chapter available on the S: drive under CPEG 210.
Quiz I to be held in two extra sessions on Sunday, November 21, at 4:00 p.m. in the DSL Lab (B108).
[Nov 1, 2010] Topic 2 material is now complete on Moodle and appears as follows:
Homework Set 2: Boolean Algebra and Logic Gates. The numbers you are responsible for in the textbook are: (2.1 through 2.9), (2.11 through 2.24), 2.27, and 2.28
R2 and R3: Reference Chapters Get your copy of the chapter available on the S: drive under CPEG 210.
[Oct 17, 2010] Topic 1 material is now complete on Moodle and appears as follows:
HPractice Set 2: Number Systems: The numbers you are responsible for are: (2, 3, 4, 5, 6), 2.3.3 (1, 2), 2-7, 2-10, 2.4.2 (1, 4, 6, 9, 10), 2-12, 2-13, 2.5.2 (1, 2, 3, 4, 5), 2.5.3 (1), 2-14, 2-15, 2-16, 2-17, 2.6.2 (1, 2, 3, 4, 6, 7, 8, 10, 11, 12), 2.6.3 (1, 2, 3), 2-19, 2-20, 2-22, 2-24, 2-25, 2-26, 2-27, 2.8.3 (1, 2 ,3 ,4 ,5 , 8, 9, 10, 11, 14, 15), 2.8.4 (1, 2), 2-31, 2.9, 2.9.3 (2 only), 2.10 .
R1: Reference Chapter Get your copy of the chapter available on the S: drive under CPEG 210.
Homework Set 1: Textbook Problems 1.4, 1.7, 1.9, 1.10, 1.12, 1.13, 1.14, 1.18, 1.20, 1.22, 1.23, 1.27, 1.29, and 1.30.