1. Course Details

  • Level: Seniors and Graduates
  • Prerequisites: EECE 421 Computer Organization or instructor’s approval
  • Lecture Times:  TT 12:30 p.m. – 2:00 p.m.
  • Student Study Hours Per Week: 9
  • Contact Hours Per Week: 3
  • Private Study Hours Per Week: 6
  • AY / Semester:  2004– 2005 / Fall
  • Professor:  Dr. I. Damaj
  • Contact Details: id01@aub.edu.lb
  • Professor's Website: http://www.idamaj.net
  • Summary of Assessment Method:  Project, 1 Quiz, 2 Assignments (Short Research Papers Review), and a Final
  • Textbook:R. Kress, “Reconfigurable Computing: Structural Programming with Reconfigurable Datapaths,” ITpress Verlag, Chicago, 1999.
  • Software Tools: MorphoSys reconfigurable computer emulator, Handel-C high-level HDL compiler (DK design suite), Xilinx ISE.
  • Hardware Devices: Xilinx FPGAs
  • References: D. Gajski, “High-Level Sythesis, Introduction to Chip and System Design” Kluwer, 1992. R. Seals, “Programmable Logic: PLDs and FPGAs,” Macmillan, 1997.

2. Aims of the Course:

This course presents the foundations of reconfigurable computing architectures and how to apply them to solving computationally-intensive problems. This includes hardware platforms and software support systems for reconfigurable computing using field programmable gate arrays. The emergence of complex reconfigurable systems is igniting a revolution in general-purpose processing. It is now becoming possible to adapt and dedicate functional units to take advantage of application dependent dataflow in order to significantly accelerate a wide variety of applications. This course will examine state-of-the-art systems that dynamically change their configuration with changing data sets and algorithm needs. Topics covered in the course include the basic concept of reconfigurable computing and its modes of operation (static vs. dynamic reconfiguration), examples of successful RC applications, existing architectures, hardware software co-design, new architectures and future trends. The course will lay a foundation for students who are interested in further studies in reconfigurable computing – reconfigurable hardware synthesis and chip design is an active area of research!

3. Short Description:

This course is of 6 chapters divided into 15 weeks. The student should be aware of the importance of revising the material on first come first serve basis. Prerequisites of this course include Computer Organization & Architecture and C programming language. The assessment is done by reviewing 2 short research papers (Ws 4 and 10), 1 design project (proposal due by W8, presentations in W15), a quiz (W9), and a final exam.

5. Assessment of the Course

Attendance 5%
Assignments and quizzes 30%
Project %30
Final 35%

Students are required to review at least two papers over the term relevant to the scope of the course. Each review should answer the following questions: