This course covers the organization of modern computer systems. In addition to learning how to program computers at the assembly level, students learn how to design the main components of a von Neumann computer system, including its instruction set architecture, datapath, control unit, memory system, input/output interfaces, and system buses. To consolidate the material presented in class, students work on assembly-language programming and datapath design assignments, and a major computer interfacing project.
A course on the organization of modern computer systems. Basic hardware and software components of von Neumann computers. Machine instruction sets and assembly language programming. Fixed- and floating-point computer arithmetic. Processor datapath and control unit design. Instruction pipelining. The memory system. Input/output interfacing techniques. System buses.
Understand the basic organization of modern computer systems.
Understand how computer programs are organized, stored, and executed at the machine level.
Understand the operation of fixed- and floating-point arithmetic units.
Analyze an instruction-set architecture and propose a suitable datapath and control unit implementation.
Understand how instruction pipelining enhances processor performance.
Understand the basic organization of the memory hierarchy.
Understand the input/output mechanisms used to connect computers to their external environments.
Understand how system buses link the components of a computer system.
|Chapters||Topics||75 Minutes Lecture||Related Sections and Assignments|
|Basic Organization of Computer Systems (ISA, Datapath, Control, Memory, I/O, Operating Systems, Compilers, Assemblers, Linkers, Loaders)
A Brief History of Computers
|2||HP: Ch. 1|
Machine Instructions and Programs
Part I: Instruction Sets and Machine Programming Models
Part II: Memory Locations, Addresses, and Operations
Part III: Assembly Language Programming (e.g. string manipulation, conditional instructions, loops, subroutine linkage, recursion)
Part IV: The MIPS Instruction Set Architecture
|HP: Ch. 2; HZV: Ch. 2; Reference Material|
Arithmetic for Computers
Part I: Fixed-Point Arithmetic and Numerical Precision
Part II: Floating-Point Arithmetic and the IEEE-754 Standard
Part III: Floating-Point Operations: addition, multiplication, and division
|HP: Ch. 3|
|Part I: Execution Performance.
Part II: Introduction to Datapath.
Part III: Control Unit Design, Single-Cycle Datapath and Control.Multi-Cycle Datapath. Hardwired Control. Microprogrammed Control. Dealing with Exceptions
|HP: Ch 4 - 5|
Part I: Instruction Pipelining;
Part II: Pipelined Datapaths; Data Forwarding; Hazard Detection; Exceptions
|3||HP: Ch 6|
Part I: The Memory Hierarchy; Semiconductor Memory Technologies (e.g. ROM, DRAM, SRAM, DDRAM, RDRAM, FLASH). Organization and Timing in DRAM chips. Memory Organization and Performance
Part II: Cache Memory (organization, block replacement policies, multi-level caches, cache performance)
Part III: Virtual Memory; TLBs; Memory Protection. Secondary Storage Devices (Floppy and Hard Disks, CDs and DVDs, Magnetic Tapes, RAID)
|HP: Ch 7|
Part I: Introduction - Buses and I/O
Part II: Bus Arbitration
Part III: I/O Devices Revisited
Part IV: Interrupts
Part V: Direct Memory Access (DMA)
Part VI: Communication Principles
|HZV: Chs. 4, 9, 10; Reference Material|
|Assignments Project and Atttendance||30%|
[June 9, 2006] The Final Grades are now available on AUBSiS.
[June 9, 2006] Quiz II grades are now posted.
[May 29, 2006] Quiz II revision is this coming Thursday at 11:00 a.m.
[May 29, 2006] Assignment 2 grades are now posted.
[May 15, 2006] Chapter 7 is posted, some parts of this chapter are reading assignments, as they were brought from computer interfacing courses.
[May 15, 2006] Quiz II is on Saturday, May 20, in Wing D at 11:25: a.m. the material includes chapters 4 and 5 (slides count). An extra session is to be given just after the quiz in room B 545.
[Apr 30, 2006] Assignment 1 grades and attendance count are now posted.
[Apr 30, 2006] Assignment 3 is posted. Due date is set to Monday 22nd of May at 5:00 p.m.
[Apr 30, 2006] Chapter 6 is posted.
[Apr 18, 2006] Quiz I Grades are posted.
[Apr 18, 2006] Assignment 2 is posted again. Due date is reset to Sunday the 30th of April at 8:00 p.m. There is no need to drop off a hard draft of your report in the box as it happened to be an open pigeonhole (there is no way to insure that your assignment will be protected there from copying and accordingly from receiving a zero after plagiarism checks).
[Apr 3, 2006] Chapter 5 is posted.
[Apr 3, 2006] Quiz I is on Thursday, April 13, in Wing D at 9:25: a.m. the material included is till chapter 4, part I (Performance) inclusive.
[Mar 25, 2006] Download solved exercises supporting chapter 3.
[Mar 25, 2006] Chapters 3 and 4 are posted.
[Mar 21, 2006] An extra session is fixed this coming Friday (24th of March) at 6:00 p.m. in room B 545. Absences will be penalized if not justified with acceptable formal reasons.
[Mar 21, 2006] Download the list of groups; any suggested changes should be emailed (latest) by this coming Friday.
[Mar 18, 2006] Assignment 1 is posted. Due date is on Friday the 7th of April at 8:00 p.m.
[Mar 18, 2006] The assignments groups (of two people) for this semester will be set this coming Tuesday, please be prepared. People failing to create a group will be assigned randomly.
[Mar 3, 2006] There will be no classes next week. Extra sessions' dates will be announced later.
[Feb 26, 2006] Chapter 2 is posted.
[Feb 6, 2006] Chapter 1 is posted.
[Feb 6, 2006] Welcome to the course website.