1. Course Details

  • Prerequisites: EECE 321 Computer Organization
  • Lecture Times:  TT 12:30 p.m. – 1:45 p.m.
  • Room: 545
  • Student Study Hours Per Week: 9
  • Contact Hours Per Week: 3
  • Private Study Hours Per Week: 6
  • AY / Semester:  2005– 2006 / Spring
  • Professor:  Dr. I. Damaj
  • Contact Details: id01@aub.edu.lb
  • Professor's Website: http://www.idamaj.net
  • Summary of Assessment Method:  Project, 2 Quiz, and a Final
  • Textbook:CDavid A. Patterson and John L. Hennessy, Computer Organization and Design: the Hardware/Software Interface, Third Edition, Morgan Kaufmann Publishers, 2004.
  • References: Carl Hamacher, Zvonko Vranesic, and Safwat Zaky, Computer Organization, Fifth Edition, McGraw-Hill, 2002. J. Bhasker, A VHDL Primer, Third Edition, Prentice-Hall, 1999.

2. Aims of the Course:

This course covers the organization of modern computer systems. In addition to learning how to program computers at the assembly level, students learn how to design the main components of a von Neumann computer system, including its instruction set architecture, datapath, control unit, memory system, input/output interfaces, and system buses. To consolidate the material presented in class, students work on assembly-language programming and datapath design assignments, and a major computer interfacing project.

3. Catalogue Description:

A course on the organization of modern computer systems. Basic hardware and software components of von Neumann computers. Machine instruction sets and assembly language programming. Fixed- and floating-point computer arithmetic. Processor datapath and control unit design. Instruction pipelining. The memory system. Input/output interfacing techniques. System buses.

4. Course Objectives and Learning Outcomes:

On successfully completing this course, students will be able to:

Understand the basic organization of modern computer systems.

  • Identify the hardware components of a computer system.
  • Explain how machine instructions and the data they operate on are represented, stored, and executed.
  • Explain the roles of the operating system, compiler, assembler, loader, and linker.
  • Identify key milestones in the evolution of computer systems.

Understand how computer programs are organized, stored, and executed at the machine level.

  • Identify the basic components of an instruction-set architecture.
  • Explain the differences between machine programming models.
  • Explain how basic arithmetic, logic, memory, and control operations work.
  • Write simple programs in MIPS R2000 assembly language.
  • Explain how subroutines are commonly linked.
  • Explain why interrupts and exceptions occur and how they are handled.

Understand the operation of fixed- and floating-point arithmetic units.

  • Represent real numbers in fixed-point notation.
  • Explain how fixed-point notations affect the dynamic range of numerical values and the precision of arithmetic operations.
  • Represent real numbers in the single- and double-precision formats of the IEEE-754 floating-point notation.
  • Demonstrate how basic floating-point arithmetic operations are performed.
  • Explain the operation of fixed-point and floating-point arithmetic circuits.

Analyze an instruction-set architecture and propose a suitable datapath and control unit implementation.

  • Identify the factors affecting execution performance.
  • Identify the steps needed to fetch and execute the machine instructions of a given instruction set architecture.
  • Identify the datapath elements needed to implement a specific instruction set.
  • Explain the principles of hardwired and microprogrammed control.
  • Design the control units for single-cycle and multi-cycle implementations of a given instruction set.
  • Explain how datapath elements and control units are implemented in hardware.
  • Measure the impact of various architectural implementation strategies on performance.
  • Explain how exceptions are handled in the control unit.

Understand how instruction pipelining enhances processor performance.

  • Explain the principle of pipelining.
  • Explain the interdependencies between instruction set design and pipelining.
  • Identify the different types of pipeline hazards.
  • Describe how different pipeline hazards affect performance.
  • Describe different techniques for dealing with pipeline hazards.
  • Measure the impact of pipelining and pipeline hazards on performance.
  • Design the datapath and control unit of a pipelined implementation of a given instruction set.
  • Describe the effect of an exception on a pipelined datapath.

Understand the basic organization of the memory hierarchy.

  • Identify the main components of the memory hierarchy.
  • Explain the differences between key semiconductor memory technologies.
  • Explain the organization of a DRAM chip.
  • Design and expand a simple memory system.
  • Explain how cache memories increase the apparent speed of memory.
  • Explain how virtual memory increases the apparent size of memory and supports the enforcement of memory protection mechanisms.
  • Explain how different secondary storage devices function.

Understand the input/output mechanisms used to connect computers to their external environments.

  • Explain the differences between program-driven, interrupt-driven, and direct memory access (DMA) input/output mechanisms.
  • Identify the components of serial and parallel input/output interface circuits.
  • Design simple input/output interface circuits.
  • Explain the operation of common peripheral communication protocols and controllers, like RS-232C, FireWire, USB 2.0, Centronix, Ethernet, Bluetooth, infrared, and WiFi.

Understand how system buses link the components of a computer system.

  • Explain how different devices coordinate the use of a bus.
  • Explain how information is transferred over synchronous and asynchronous buses.
  • Explain the operation of common bus protocols like PCI, and SCSI.
Chapters Topics 75 Minutes Lecture Related Sections and Assignments
Chapter 1:
Computer Abstractions
Basic Organization of Computer Systems (ISA, Datapath, Control, Memory, I/O, Operating Systems, Compilers, Assemblers, Linkers, Loaders)
A Brief History of Computers
2 HP: Ch. 1
Chapter 2:
Machine Instructions and Programs
Part I: Instruction Sets and Machine Programming Models
Part II: Memory Locations, Addresses, and Operations
Part III: Assembly Language Programming (e.g. string manipulation, conditional instructions, loops, subroutine linkage, recursion)
Part IV: The MIPS Instruction Set Architecture

HP: Ch. 2; HZV: Ch. 2; Reference Material
Chapter 3:
Arithmetic for Computers
Part I: Fixed-Point Arithmetic and Numerical Precision
Part II: Floating-Point Arithmetic and the IEEE-754 Standard
Part III: Floating-Point Operations: addition, multiplication, and division
HP: Ch. 3
Chapter 4:
The Processor
Part I: Execution Performance.
Part II: Introduction to Datapath.
Part III: Control Unit Design, Single-Cycle Datapath and Control.Multi-Cycle Datapath. Hardwired Control. Microprogrammed Control. Dealing with Exceptions
HP: Ch 4 - 5
Chapter 5:
Part I: Instruction Pipelining;
Part II: Pipelined Datapaths; Data Forwarding; Hazard Detection; Exceptions
3 HP: Ch 6
Chapter 6:
Part I: The Memory Hierarchy; Semiconductor Memory Technologies (e.g. ROM, DRAM, SRAM, DDRAM, RDRAM, FLASH). Organization and Timing in DRAM chips. Memory Organization and Performance
Part II: Cache Memory (organization, block replacement policies, multi-level caches, cache performance)
Part III: Virtual Memory; TLBs; Memory Protection. Secondary Storage Devices (Floppy and Hard Disks, CDs and DVDs, Magnetic Tapes, RAID)
HP: Ch 7
Chapter 7:
Computer Interfacing
Part I: Introduction - Buses and I/O
Part II: Bus Arbitration
Part III: I/O Devices Revisited
Part IV: Interrupts
Part V: Direct Memory Access (DMA)
Part VI: Communication Principles

HZV: Chs. 4, 9, 10; Reference Material

6. Assessment of the Course

Assignments Project and Atttendance 30%
Quiz I 20%
Quiz II 20%
Final 30%

[June 9, 2006] The Final Grades are now available on AUBSiS.

[June 9, 2006] Quiz II grades are now posted.

[May 29, 2006] Quiz II revision is this coming Thursday at 11:00 a.m.

[May 29, 2006] Assignment 2 grades are now posted.

[May 15, 2006] Chapter 7 is posted, some parts of this chapter are reading assignments, as they were brought from computer interfacing courses.

[May 15, 2006] Quiz II is on Saturday, May 20, in Wing D at 11:25: a.m. the material includes chapters 4 and 5 (slides count). An extra session is to be given just after the quiz in room B 545.

[Apr 30, 2006] Assignment 1 grades and attendance count are now posted.

[Apr 30, 2006] Assignment 3 is posted. Due date is set to Monday 22nd of May at 5:00 p.m.

[Apr 30, 2006] Chapter 6 is posted.

[Apr 18, 2006] Quiz I Grades are posted.

[Apr 18, 2006] Assignment 2 is posted again. Due date is reset to Sunday the 30th of April at 8:00 p.m. There is no need to drop off a hard draft of your report in the box as it happened to be an open pigeonhole (there is no way to insure that your assignment will be protected there from copying and accordingly from receiving a zero after plagiarism checks).

[Apr 3, 2006] Chapter 5 is posted.

[Apr 3, 2006] Quiz I is on Thursday, April 13, in Wing D at 9:25: a.m. the material included is till chapter 4, part I (Performance) inclusive.

[Mar 25, 2006] Download solved exercises supporting chapter 3.

[Mar 25, 2006] Chapters 3 and 4 are posted.

[Mar 21, 2006] An extra session is fixed this coming Friday (24th of March) at 6:00 p.m. in room B 545. Absences will be penalized if not justified with acceptable formal reasons.

[Mar 21, 2006] Download the list of groups; any suggested changes should be emailed (latest) by this coming Friday.

[Mar 18, 2006] Assignment 1 is posted. Due date is on Friday the 7th of April at 8:00 p.m.

[Mar 18, 2006] The assignments groups (of two people) for this semester will be set this coming Tuesday, please be prepared. People failing to create a group will be assigned randomly.

[Mar 3, 2006] There will be no classes next week. Extra sessions' dates will be announced later.

[Feb 26, 2006] Chapter 2 is posted.

[Feb 6, 2006] Chapter 1 is posted.

[Feb 6, 2006] Welcome to the course website.