EECE 421: Computer Architecture

• Level: Seniors and Graduates
• Prerequisites: EECE 321 Computer Organization
• Lecture Times:  TT 12:30 p.m. – 1:45 p.m.
• Room: 543
• Student Study Hours Per Week: 9
• Contact Hours Per Week: 3
• Private Study Hours Per Week: 6
• AY / Semester:  2005– 2006 / Fall
• Professor:  Dr. I. Damaj
• Contact Details: id01@aub.edu.lb
• Professor's Website: http://www.idamaj.net
  
• Summary of Assessment Method:  2 Quiz, Assignments, and a Final
  
• Textbook:Computer Architecture: A Quantitative Approach, Third Edition, Hennessy and Patterson, Morgan Kaufmann Publishers (Elsevier), 2002.
  
• References: Parallel Computer Architecture: A Hardware/Software Approach, Second Edition, Culler, Singh, and Gupta, Morgan Kaufmann Publishers (Elsevier), 1999. David A. Patterson and John L. Hennessy, Computer Organization and Design: the Hardware/Software Interface, Third Edition, Morgan Kaufmann Publishers, 2004. Introduction to Parallel Processing: Algorithms and Architectures. Behrooz Parhami, Plenum 1999. Computer Architecture: From Microprocessors to Supercomputers, Oxford University Press, 2005, ISBN 0-19-515455-X
  

A course on the principles, techniques, and trade-offs used in designing modern processor architectures. Topics include: benchmarking and performance evaluation, long-latency instruction pipelining, hardware and software techniques for exploiting instruction-level parallelism (out-of-order, speculative, and predicated instruction execution; multithreading; loop unrolling, software pipelining, and trace scheduling), high performance memory systems, and multiprocessor systems and programming.

• Identify the basic factors affecting performance, explain the role of benchmark suites in evaluating performance, and use appropriate metrics to compare and summarize processor performance.
• Identify how variable-latency execution units are supported in a long-latency pipeline, the hazards that arise in such pipelines, and techniques for dealing with them.
• Define instruction-level parallelism and the different types of instruction dependencies.
• Explain how the datapath and control structures like Tomasulo’s Algorithm support out-of-order instruction execution.
• Identify different strategies for dynamic instruction scheduling, and explain their trade-offs, side-effects, and impact on performance.
• Explain how various compiler techniques expose instruction-level parallelism, and measure their impact on performance and code size.
• Explain hardware and software techniques for supporting predicated instruction execution.
• Explain how different techniques increase the performance and bandwidth of the memory system.
• Identify different types of multiprocessor architectures.
• Explain the characteristics of typical multiprocessor applications.
• Explain different cache coherency techniques.
• Explain different inter-process communication and synchronization techniques.
• Explain the role of parallel programming languages and parallelizing/vectorizing compilers.
• Develop high-performance processor models using SimpleScalar, VHDL/Verilog, and/or C++.